In comparison to devices in bulk silicon, SOI devices offer improved speed performance resulting from reduced parasitic capacitance, simplified device isolation and design layout, and radiation hardness for space and nuclear applications. Furthermore, because the SOI devices are dieletrically isolated, they are latch up free in CMOS circuits and are useful for high-voltage integrated circuits.
The fabrication of silicon-on-insulator (SOI) lateral bipolar transistors has provided high speed devices for various circuit applications. Bipolar transistors are important for SOI integrated circuit technology since they can handle high frequency switching capabilities. SOI bipolar transistor can have five terminals with n-p-n or p-n-p structures formed on an insulator with a front gate centered above the base and a rear gate using the bulk semiconductive wafer on which the insulator is formed. These devices have been fabricated using standard polysilicon gate CMOS processing and are compatible with SOI-MOS devices.
A SOI bipolar transistor is described in Sturm, James C. et al. "A Lateral Silicon-on-Insulator bipolar transistor With a Self-Aligned Base Contact", IEEE Electron Device Letters, Vol. EDL-8, No. 3, March, 1987.
The fabrication steps of the device described by Sturm et al. above include the recrystallization of polycrystalline silicon film on a thermal oxide layer to form a thin silicon film that is free of subgrain boundaries. The silicon is then uniformly doped with boron and provided with a second heavily doped boron region near the surface. An etching step is used to isolate the gate area as a pedestal.
Arsenic ion implantation and annealing are then used to form the emitter and collector regions on either side of the silicon pedestal in the base.
The heavy doping at the top of the base pedestal serves two purposes. First, it provides a low-resistance ohmic contact. Second, it provides a built-in electric field which repels minority-carriers (electrons) away from the metal base contact. Electrons reaching the base contact would recombine and give rise to base current, not the collector current desired in normal bipolar transistor operation.
There are two problems with this approach, however. First, this approach is specific to this device and is not compatible with CMOS processing. Secondly, there is the absence of a lightly doped collector region. Such a region is necessary for minimizing the base-collector capacitance.